The development of efuse technology is based on the characteristics of polysilicon fuse. The initial resistance of an efuse is considerably small, but when a high current flows through the efuse, the efuse may be melted and the resistance multiplies. Therefore, the value of the data programmed to an efuse memory cell may be reflected by whether the efuse is melted.
As shown in FIG. 1, an existing efuse memory circuit often includes m wordlines, n column-select transistors, n bitlines, n sense amplifiers (SAs), and an efuse memory array, where m and n are positive integers.
The m wordlines include: a first wordline WL1, a second wordline WL2, . . . , and an mth wordline WLm. The n column-select transistors include: a first column-select transistor M1, a second column-select transistor M2, a third column-select transistor M3, . . . , and an nth column-select transistor Mn. Each source of a column-select transistor is connected to the power supply voltage VDD.
The n bitlines include: a first bitline BL1, a second bitline BL2, a third bitline BL3, . . . , and an nth bitline BLn. Each one of the n bitlines is connected to the drain of the corresponding column-select transistor in the n column-select transistors.
The n sense amplifiers include: a first sense amplifier SA1, a second sense amplifier SA2, a third sense amplifier SA3, . . . , and an nth sense amplifier SAn. Each sense amplifier is connected to the corresponding bitline in the n bitlines.
That is, an efuse memory array may include an array of m (row)-by-n (column) memory cells. Each one of the m wordlines corresponds to one of the m rows of memory cells: each one of the n bitlines corresponds to one of the n columns of memory cells; and each memory cell corresponds to one wordline and one bitline.
Each memory cell includes a row-select transistor and an efuse. The gate of the row-select transistor is connected to the wordline corresponding to the memory cell, and the drain of the row-select transistor is connected to the first terminal of the efuse. The source of the row-select transistor is grounded (GND), and the second terminal of the efuse is connected to the bitline corresponding to the memory cell. For example, the memory cell 10 at (row 1, column 1) corresponds to the first wordline WL1 and the first bitline BL1. Memory cell 10 includes a row-select transistor M0 and an efuse F0. Of the row-select transistor M0, the gate is connected to the first wordline WL1, the drain is connected to the first terminal of the efuse F0, and the source is grounded. The second terminal of the efuse F0 is connected to the first bitline BL1.
The ON/OFF state of the a column-select transistor is controlled by applying a gate voltage on the column-select transistor, and the ON/OFF state of row-select transistors in a same row may be controlled by applying a voltage on the corresponding wordline. When the row-select transistor of a memory cell and the column-select transistor corresponding to the memory cell are both on, the efuse of the memory cell will be melted. The operation of melting an efuse is referred as a “write” operation to the memory cell. Whether an efuse is melted may be detected by testing the resistance of the efuse. When the resistance is higher than a certain threshold value, the efuse is considered melted, otherwise the efuse is considered not melted (i.e., the write operation to the memory cell fails).
Because a memory cell may not be written again once the efuse of the memory cell is melted, a memory cell may only be written once. The data often needs to be written to the memory cell is “1”. That is, the efuse of the memory cell needs to be melted when “1” is to be stored into the memory cell. When “0” is to be stored into a memory cell, the efuse of the memory cell does not need to be melted.
However, writing a memory cell may be susceptible to programming failure, often caused by failing to melt the efuse after a “write” operation to the memory cell. The programming failure may result in an error when storing data to the memory cell. The programming error may further lead to reading error and, consequentially, low manufacturing yield of the corresponding memory device.
Build-in self repair (BISR) technique has been widely used to repair memory arrays. Often, a reconfigurable BISR scheme, e.g., a redundant circuit, to provide redundancy such that when programming failures and/or reading errors occur, the memory array may still operate with desired accuracy. In existing efuse technology, when a writing failure occurs in a memory cell of a row/column, the memory cells of the entire row/column may often need to be replaced. Certain redundancy techniques require a large area on the memory array or corresponding chip for redundancy circuits. Manufacturing yield of the memory array is undesirably low.